搭建一款棋牌app多少钱
Sort by
  1. Language:Verilog
  2. Category:All
  3. Time:ALL
  4. View:All
Remove all
Language More Hide
Category More Hide
Time
View
More

AXI slave verilog code

Wrote AXI slaver Verilog code, hope to give you some inspiration...

Verilog Jpeg Encoder

This core takes as an input the red, green, and blue pixel values, like from a tiff image file, and creates the JPEG bit stream necessary to build a jpeg image. The core was written in generic, regular Verilog code that can be targeted to any FPGA. The core does not rely on any proprietary IP cores,...

FFT FFT algorithm based on Verilog

This code implements 128 points, FFT calculation of 16-bit integers, Quartus II version 8.0, as verified by simulation, timing constraints and practical verification program features can fully meet demand under normal circumstances, clocking 150Mhz....

Histogram equalization FPGA implementation

Real-time image histogram equalization in FPGA, effective use of FPGA chip-chip resources, no need to add external memory chips. The code is based on YCbCr, actually only the luminance histogram equalization, time after which a synchronous CB,CR color components, avoiding partial color problem! Code...

HDMI interface chip (ADV7513) drive, 1080p60,720p60 colour bar test!

This engineering achieved has HDMI chip of configuration and drive test, can selective configuration for 1080P60,720p60,ddrmode, mode, 1080p60 and 720p60 format of video image now is mainstream format, and ddrmode can greatly save FPGA Shang valuable of tube feet resources, this engineering can sele...

DDR2 controller, Verilog source code

Using Verilog prepared of DDR2 controller, achieved has DDR2 of reads and writes function, in Xilinx vietex5 Shang to achieved, achieved has Imaging algorithm in the of data turn home,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,...

The DMAC module in AMBA Bus based on SOC design

This design is based on the SOC system, using AMBA Bus DMA data transfer mode control module design of DMAC, a total of five modules, proven design timing constraints and other requirements...

Booth multiplier in verilog

This file describes the code for booth multiplier in verilog. the source code is simulated and verified for better results...

Flash controller verilog code

This is the verilog code of Samsung K9 series Flash controller, it is complied and verified on FPGA development board, the verification environment is quartusii and modelsim combined platform. You can find the datasheet of K9 flash on the internet. The size of the flash is 1024*32....

1024-bit RSA encryption algorithm

Description of the RSA algorithmSelect two large prime numbers with the same length, p and q , Calculate the product:n = pqThen pick a random encryption key, make e, (p-1) (q-1) are prime numbers from each other.Finally, calculate the decryption key d use Euclid extended algorithm to meet the requ...

prev 1 2 3 4 5 6 7 8 9 10 ... 80 next

LOGIN

Don't have an account? Register now
Need any help?
Mail to: [email protected]

切換到中文版?

CodeForge Chinese Version
CodeForge English Version

Where are you going?

^_^"Oops ...

Sorry!This guy is mysterious, its blog hasn't been opened, try another, please!
OK

Warm tip!

CodeForge to FavoriteFavorite by Ctrl+D
搭建一款棋牌app多少钱 广东36选7开奖号3 重庆快乐十分电视开奖 老版紫微倒数 亲朋棋牌充值中心网页 安徽十一选五助手下载 浙江舟山飞鱼彩票控 河北时时彩现场开奖结果 黑龙江体育彩票11选5 浙江20选5预测号码 河南十一选五下载